# 获取脚本所在路径
set script_dir  [ file dirname [ file normalize [ info script ] ] ]

# ROOT 所在路径
set root_dir  [ file normalize "$script_dir/../.." ]

# 所有工程所在文件夹
set builds_dir  [ file normalize "$root_dir/build" ]

# NutShell 所在文件夹
set nut_dir  [ file normalize "$root_dir/NutShell" ]

# 加载板子和芯片信息
source $script_dir/board.tcl

# Add files for system top
set src_files [list "[file normalize "$nut_dir/src/test/vsrc/monitor.v"]"]

# vivado 工程所在文件夹名
set project_dir $builds_dir/pynq

# vivado 工程名 
set project_name test

# 创建工程
create_project $project_name -force -dir $project_dir/ -part ${device}

# 配置板子信息
if {[info exists board]} {
    set_property board_part $board [current_project]
}

# 加入 lib 文件
set inc_files [list "[file normalize "${nut_dir}/fpga/lib/include/axi.vh"]"]
add_files -norecurse -fileset sources_1 $inc_files
set_property is_global_include true [get_files $inc_files]

# 加入由 chisel 生成的 Verilog 文件
lappend src_files "[file normalize "${nut_dir}/build/TopMain.v"]"

# 加入约束文件
if {[info exists xdc_files]} {
    add_files -norecurse -fileset constrs_1 $xdc_files
}

# 生成 block design
source ${script_dir}/standalone.tcl
save_bd_design
# $design_name 是在 ${script_dir}/standalone.tcl 中定义的
close_bd_design $design_name

# 写综合检查点
set_property synth_checkpoint_mode Hierarchical [get_files *${design_name}.bd]

# 生成 wrapper
make_wrapper -files [get_files *system_top.bd] -top

# 添加 wrapper
add_files -norecurse -fileset sources_1 $project_dir/$project_name.srcs/sources_1/bd/system_top/hdl/system_top_wrapper.v
set topmodule system_top_wrapper

# setting top module for FPGA flow and simulation flow
set_property "top" $topmodule [current_fileset]

# setting Synthesis options
set_property strategy {Vivado Synthesis defaults} [get_runs synth_1]
# keep module port names in the netlist
set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY {none} [get_runs synth_1]

# setting Implementation options
set_property steps.phys_opt_design.is_enabled true [get_runs impl_1]

# update compile order 
update_compile_order -fileset sources_1